Dynamic power consumption is an ongoing concern for integrated circuit (IC) devices, especially with the ever-increasing clock frequencies used in synchronous IC devices. One known technique to reduce the dynamic power consumption of clock distribution networks is to employ clock-gating circuits (CGC) that selectively gate a number of clock signals on the IC device. More specifically, clock-gating circuits may reduce power consumption by selectively disabling portions of the clock tree so that circuit elements such as latches and/or flip-flops (FFs) associated with the disabled portions do not switch between logic high and low states. Preventing such latches and/or FFs from toggling between their respective logic states may significantly reduce dynamic power consumption of the IC device.
Clock-gating is performed at a fine-grained register-group level, whereas power gating is performed globally at an entire hardmacro (or) subchip level. Clock-gating is implemented in hardware for processors or accelerators based on the functional activity during respective clock cycles in the particular logic design. At such fine-grained level, clock-gating reduces the dynamic power.